The present invention relates generally to the field of oscillators, and, in particular, to improvements in crystal-controlled CMOS data clock oscillators which must meet stringent square wave output specifications.
Modern semiconductor technology has made possible the development and production of highly stable reference oscillators for a wide variety of electronic equipment. Data clock oscillators, utilizing complementary metal-oxide-semiconductor (CMOS) technology, have been widely used in various timing applications over the frequency range of 0.5 MHz to 30 MHz. The stringent electrical specifications for such data clock oscillators include: operation over a wide temperature range (-40.degree. C. to +85.degree. C.); high frequency stabilities (+/-100 parts per million); low power consumption (100 milliwatts); supply voltage operating range (4.5 to 5.5 VDC); and precise duty cycle control.
Although many data clock oscillator applications only require a nominal 40%-60% duty cycle, several computer or communications-based IC designs now require a more precise duty cycle within at least a 45%-55% tolerance. Such a requirement is specified for the Motorola MC68000 series microprocessors. Furthermore, certain microprocessor applications require even tighter specifications, such as 50% +/-3% symmetry.
Several alternatives exist to achieve precise duty cycle control. It is well known that a perfectly symmetrical duty cycle can be achieved by operating the oscillator at some multiple of the desired output frequency, and then dividing the oscillator output signal by means of a digital divider circuit. Hence, in integrated circuit designs, the oscillators often run at twice the required frequency, and the output is then fed to a flip-flop to achieve an accurate 50% duty cycle. However, this divider approach limits the upper frequency boundary that can be achieved with a crystal resonator operating in the fundamental mode. The additional divider circuitry also significantly increases the cost and complexity of the oscillator--solely to achieve an accurate duty cycle.
A second approach for achieving a more accurate duty cycle output is the addition of an automatic gain control (AGC) circuit with a sine-to-square wave conversion circuit. The AGC would compensate for variations in supply voltage V.sub.CC, temperature variations, and integrated circuit processing variations, and the low-level output signal would then be converted to the required square wave. An AGC circuit, however, tends to degrade the signal-to-noise (S/N) performance of the oscillator, since the AGC requires small signal amplitudes to operate. This degradation is in addition to the obvious cost and complexity disadvantages of additional AGC circuitry.
The prior art also teaches that the use of complementary-type transistors, i.e., PNP/NPN or P-channel/N-channel, between the power supply voltage V.sub.CC and ground voltage V.sub.SS, improves the output waveform symmetry. Moreover, it is also known that the threshold voltages V.sub.T of MOS transistors, which are part of one and the same integrated circuit, tend to track each other over temperature and process variations. Hence, using a combination of these approaches, the waveform symmetry then becomes dependent upon the tracking characteristics of the output CMOS stage. Although presently available CMOS data clock oscillators can surpass the minimal specifications of frequency tolerance, temperature stability, and supply voltage rejection, unfortunately, they often fail to meet the stringent duty cycle requirement of 50% +/-5%.
A need, therefore, exists for a simple, cost-effective, data clock oscillator which exhibits accurate output symmetry over variations in frequency, temperature, supply voltage, and processing.